System for synchronizing a receiver and transmitter at opposite ends of a transmission path and for evaluating the noise level thereof



wnlwww wf V . F. w. MALLoY 3,491,338 SYSTEM FOR SXNQ'HRONLZING ARECEIVER AND TRANSMITTER Jan. 20, 1970 ATl (')PPOSITE ENDS OF ATRANSMISSION PATH AND FOR EVALUATING THENOISE LEVEL THEREOF 7Sheetssheet 11 Filed April 17, 1967 Jan. 20, '1970 lF. w. MALLoY SYSTEMVFIOR SYNCHRONIZING A RECEIVER AND TRANSMITTER AT OPPOSITE ENDS OF ATRANSMISSION PATH AND FOR EVALUATING THE NOISE LEVEL THEREOF '7Sheets-Sheet 2 Filed April 17. 1967 Jan'. 20, 1970 F. w. MALLoY SYSTEMFOR SYNCHRONIZING A RECEIVERAAND TRANSMITTER AT OPPOSITE ENDS OF ATRANSMISSION PATH AND FOR EVALUATING THE NOISE LEVEL THFREOF 7Sheets-Sheet 5 Filed April 17. 1967 h III. III- Jan. 20, 1970 F. w.MALLOY 3,491,338

SYSTEM FOR SYNCHHONIZINC' A RECEIVER AND TRANSMITTER, AT OPPOSITE ENDSOF A TRANSMISSION PATH AND FOR EVALUATING THE NOISE LEVEL THEREOF FiledApril 17, 1967 7 Sheets-Sheet 4 1N VENTOR. FM/Yc/J a4/VAMOS* BY I J. yl/

Jam 26, g@ F. w. MALLOY 3,4%,338

SYSTEM FOR SYNCHRONTZING A RECEIVER AND TRANSMITTER AT OPPOSITE ENDS OFA TRANSMISSION PATH AND FOR EVALUATING THE NOISE LEVEL THEREOFllllllllllllllllllllIllllllll-llllllllllllllllllllllllllllllllllllllilllllllllllllllllllllllllllllllll mafwf l l l l lA vll` ,l lvl l L r L l L I 1 x 1|L 1 Ln u 1r y Al4 l l l Y l I 1 Jan. 2Q,1976 F. w. MALLOY 3,491,338 l SYSTEM FOR SYNCHRONIZING A RECEIVER ANDTRANSMITTER AT OPPOSITE ENDS OF A TRANSMISSION PATH AND FOR EVALUATINGTHE NOISE LEVEL THEREOF Filed April l?. 1967 7Sheets-Sheet 6 il k l k QuQL un n Hug mi a #a gw g@ 5 w s kga @s *M mu@ fla f J FE lllvl jbl/oa/af//aa/a//faa/aaaa/m/aaa//w/ Malacca/)0l INVENTOR. PRH/VCH M MALA 0y Jan. 20, 1970 F. w. MALLOY 3,491,338

SYS'lEM FOR SYNCHRONIZING A RECEIVER AND TRANSMITTER,

OPPOSITE ENDS oF A TRANSMISSION PATH AND NOR VALUATINC THINOSE LEVELTHREOT" Filed April 17.1957 7 sheets-sheet s' L l l 3,491,338 SYSTEM FORSYNCHRGNIZING A RECEIVER AND TRANSMETTER AT OPPUSITE ENDS F ATRANSMHSSION PATH AND FOR EVALU- A'HNG THE NOISE LEVEL THEREOF FrancisW. Malloy, Wayland, Mass., assignor to the United States of America asrepresented by the Secretary of the Air Force Filed Apr. 17, 1967, Ser.No. 632,160 Int. Cl. G08b 29/00, 1/00; G06f 11/00 US. Cl. Mtl- 146.1 4Claims ABSTRACT 0F THE DISCLSURE A communication synchronizing andtesting system for producing a series of synchronizing pulses andautomatically followed by a series of test pulses formed by a ipflopchain and a matrix network which feed the test pulses to a shiftregister which is controlled by a shift generator acting as a delaycircuit. The output of the shift register is fed to an evaluator unitand if there are minimum errors, a GO signal is generated.

This invention relates to communications, and more particularly to thesynchronization and testing of transmission between two stations.

This invention fills the need for very reliable long-rangecommunications between aircraft and ground stations. Conventional highfrequency propagation has been plagued with absorption diicultiesresulting in radio blackout in the auroral belt 0f the northern regionsof this continent (aurora borealis), and noise largely caused bymagnetic radiation.

The invention is an electronic device designed to perform Vthreefunctions necessary for the proper operation of electronic units such astiming units and converters associated Iwith the two stations, such asone land-based and the other airborne, involved in the transmission. Itfirst produces a baud synchronizing signal which synchronizes thetransmitter and receiver timing units in each leg of the system, ofwhich there are four; one at the ground transmitter, one at the groundreceiver, and one each with the airborne transmitter and receiver.

Its secon-d function is to produce a multi-digit preamble inpredetermined patterns of ones (ls) and zeros (Os).

Third, when this preamble is stored and then processed by an evaluatorunit, an enabling voltage is produced or, under certain conditions, isnot produced. This enabling voltage results in a GO signal which placesthe transmitter in a readiness to process the data supplied to it from ateletypewriter or other source of information by activat-1 ing the ringcounters of the converters or other circuitry.

It `is therefore an object of the invention to provide reliablesynchronization between two widely separated communication stations.

It is another object to provide a system for evaluating the transmissionpath between two stations to determine whether the noise level issuiciently low to permit reliable communications.

The above and still other objects, advantages and features of myinvention will become apparent upon consideration of thefollowingdetailed description taken in connection with the illustrative'embodiments in the accompanying drawings, wherein:

FIG. 1 is a block diagram of the baud sync generator with .a circuit ofa three-input OR gate;

FIG. 2 is a block diagram of the preamble generator;`

FIG. 3 is a block diagram of the shift register and shift'- FIGS. 5 7are waveform diagrams useful in the expla# nation of the invention. iThefggeneration of a synchronization signal for .the transmission to theremote receiver site isa first function of this invention. Referring toFIG. l, start pulse 11 is generated at the control console and*amplified by pulse amplifier 13. This pulse triggers clock gate controlflipflop 17 which enables gated amplifier 19 into the set state viadiode gate 15. Baud clock pulses may be supplied from either receiverbaud clock generator 21 or transmitter baud clock generator 23 ascontrolled by switch 25 Iwhich is one section of the transmitreceiveswitch. Baud clock generators 21 and 23 can be standard multivibratorsand are commercially and readily available. The clock pulses areamplified by pulse' amplifier 27 and are passed by gated amplifier 19 tothe '{first flip-flop stage 29 of the baud sync generator. An output istaken from one side of flip-flop 29 and connected to one input of tripleinput OR gate 35. OR gate 35 comprises diodes 42, 43 and 44, transistor47 and resistors 49 and 50. The output of OR gate 35 which is sent tothe transmitter is taken from emitter 53. Visual indication of baud syncgenerator is given by flashing light 110 on the panel of indicator unit109 (FIG. 3). The remaining Hip-flops collectively designated as 31'inthe chain are; used to produce a predetermined delay. Pulses to theflip-flop are gated by gated amplifiers 41 and are steered by'diodegates 33. A pulse delayed for a predetermined time from the start pulseis taken from final pulse amplifier 45. This pulse performs threefunctions: (1) it triggers clock gate control 17 into its reset state,thus inhibiting gated amplifier 19 which cuts off the baud clockpulsetrain used as a synchronizing signal. By this means a synchronizingpulse train for the predetermined timed at the baud clock rate isgenerated for transmission to the remote receiver site; (2) as shown inFIG. 2, clock gate control 57 is triggered into its set state via diodegate '55; and (3) the pulse delayed for a predetermined time triggersthe shift gate control flip-op 97 into its set state via `diode gate 9Sshown in FIG. 3. Flip-flop 97 is a component of the shift generatorwhich will later be fully explained.

The second function of the invention is to generate a multi-digit pulsetrain which is called -a preamble. In the embodiment the invention isexplained using a 49- digit pulse train. This preamble, which was theresult of intensive research and calculation, is virtually impossible toreproduce accidentally as, for example," by excessive and erratic noisein the transmission path between the ground and the aircraft. Referringto FIG. 2, when the system 'isin the transmit mode and the delayed pulsefrom pulse amplifier 45 triggers clock gate control 57 into the setstate via diode gate 55, clock gate amplifier 59 is enabled and baudclock pulses are passed on to the flip-flop chain of the preamblegenerator which comprises flip-flops 61- 66 and their associated diodegates 69 and gated amplifiers 71. Clock gate control 57-can be astandard ipflop module which is commercially and readily available. Theip-op chain is a six-stage counterfwhich counts sequentially to binary64 and is then reset by pulse from reset gated amplifier 73. The outputwaveforms from each of the six stages are standard counter waveforms andare 'shown on the timing diagram of FIG. 5. Both the zero and oneoutputs of the first three ip-op stages 61- 63 of the counterareconnected to the input of matrix 75 and the outputs of the last threeip-fiops 64-66 are connected to the inputs of matrix 76.

Referring.; to EIG. 4 which shows the details of the matrices, matrix.fis a 6 x 8 (6 inputs-eight outputs) rectangular minimal design matrixswitch which is con trolled by the zero and'aone outputs of flip-flops61-63 of the six-stage binary counter of the preamble generau tor. Eachof the 8 legs of matrix 75 is a triple input AND gate performing alogical AND function in response to stimuli from the logical one andlogical zero outputs of the associated flip-Hops. When all three inputsof any one of the eight AND gates comprising matrix 75 are high, thatis, energized `by a logical one, the output of the gate is high. lf anyof the three inputs of a gate are energized by a logical zero, theoutput of that gate is low. If negative logic is employed, a high orlogical one is defined by a negative voltage and constitutes an enablelevel or trigger depending on the use to which it is put. A low isdefined as ground and constitutes an inhibit or disable level or anotrigger, again depending on the use to which it is put. As used inthis system, the output of matrices 75 and 76 are in either enablelevels or inhibit levels for matrix 77. Matrix 76 is exactly the sametype as matrix '75 except that it has only 7 outputs. It is also arectangular minimal design matrix which has l inputs, 8 from matrix 75and 7 from matrix 76, and has 25 outputs. Each of the 25 legs of thematrix 77 is a dual input AND gate. One of the two inputs of any of thegates is energized Yby an output from matrix 75 and the other input isenergized from an output from matrix 76. Coincidence at a gate, that is,when both inputs of that gate are high, produces an output. As anexample, when output 1 of matrix 75 and output 1 of matrix 76 are bothhigh, the two inputs of the dual input of AND gate of leg 1 of matrix 77are enabled coincidentally and an output results. This output representsthe first one digit of the preamble. At leg 2 of matrix 77 there iscoincidence between output 1 of matrix 76 and output 2 of matrix 75,producing the second 1 digit of the preamble. The third l digit resultsfrom coincidence between output 1 of matrix 76 and output 3 of matrix75. The fourth digit of the preamble is a zero and results from theanti-coincidence ybetween output 1 of matrix 76 and output 6 of matrix75. In this manner the remaining digits of the preamble are produced ina predetermined sequence. Reference to the timing diagram of FIG. 6 willfacilitate understanding of the logic used to produce the desired49-digit preamble. An-output of matrix 77 is fed to the shift registerthrough switch'82, a section of the transmitreceive switch. Anotheroutput is fed to reset gated amplifier 73 via emitter follower 74.

The rectangular waveform of matrix 77 output is coupled via OR gate 81through an emitter follower 83 to the gain level input of gatedamplifier 85. The pulse input to gated amplifier 85 is baud clock pulsesand the output is the coded preamble of the system. The preamble is thenfed to emitter follower 87 which is coupled to one input of triple inputOR circuit 3S (FIG. 1).

The second leg of the dual output of gated amplifier 35 is connected toselector switch 84 (a section of the transmit-receive switch). When thesystem is in the transmit mode the preamble as shown in FIG. 3 iscoupled through read gate 91 to the pulse input of fiip-flop 93 viadiode gates 94 which are stages of a l9i-stage shift reg'- ister.

The third function, as previously mentioned, of the pulse delayed for apredetermined time and emanating from pulse amplifier 45 is to triggerthe shift generator. The pulse triggers shift gate control 97 into theset state via diode gate 95, thus enabling shift clock gated amplifier99 which then passes shift pulses via shift multivibrator 101 and pulseamplifiers 103 to 105 to the shift pulse input of the first stage of theshift register. The shift generator starts simultaneously with thepreamble generator. Referring to the waveform diagram of FIG. 7, clockpulses shown at 121 gated through clock gated amplifier 99 triggermonostable multivibrator 101 producing rectangular lwave shown at 123.This is differentiated producing the wave 125 and the wave shown at 127is produced. Differentiation of rectangular pulses 123 can beaccomplished by pulse amplifier 103-10'5 which, being edge sensitive,produces a sharp pulse for each edge either positive going or negativegoing of the rectangular pulses that produce it. This system provides adelay cir` cuit in which clock pulses are delayed. After amplification,the delayed pulse train is used as a shift pulse train for the shiftregister. An enable signal shown at 118 is taken from matrix 77 and usedto gate a pulse shown at 119 through shift reset gated amplifier 96 viaemitter follower 98. This pulse is the reset for the shift register. Thecoded preamble is then inserted serially into the shift register untileach preamble stage contains one digit of the 49-digit preamble. Thepreamble will remain stoi'ed in the shift register indefinitely untilthe shift register is cleared by activating remote reset 108 on theconlrol console which is amplified by reset pulse amplifier 107. Visualindication of the stored preamble is given by lights on indicator panel109.

If the stored preamble is error-free and no errors are allowed in thepreamble in the transmit mode for properly functioning equipment, theevaluator unit which samples the waves of each of the 98 pulses from theshift register generates a pluse designated as a GO pulse of the systemthrough enable/disable flip-op 113. The evaluator unit consists of ORgates 112 and differential amplifier 111 which is conventional in theart. Forty-nine (49) of the OR gates are connected to the logical oneoutput of the shift register, and 49 are connected to the logical zerooutputs. The gates function as summing circuits, summing up voltages ofthe one and zero outputs separately. The resultant voltage levels of theone and zero pulses act as bias voltages applied to differentialamplifier 111. Since the output of a differential amplifier isproportional to the difference between the voltage levels applied to thetwo inputs, that is, Eout=K (E0-E1) an error occurring in the preamblewill cause a reduction in the output level of the amplifier. The biascontrol can be so set that when more than a given number of errors, suchas three, are present in the preamble, the amplitude of the output pulseof the differential amplifier i's too low to activate enable/disableflip-flop 113. This constitutes a NO-GO signal and the converter orother circuitry willlnot receive or transmit a message depending on theposition of switch 114 (a section of the transmit-receive switch) underthese conditions. When fewer than the allowed errors arev present in thepreamble, the amplitude of the output pulse of the differentialamplifier is sufiiciently high to activate flip-fiop 113 causing it tochange states, applying an enable level to an AND gate in the converteror other circuitry. This constitutes a GO signal and the converter willeither transmit a message or receive one, depending upon which mode thissystem is in.

The system can be switched to the receive mode with the transmit-receiveswitch which is a ganged switch comprisi'ng sections 25, 48, 82, and 84.When the transmitreceive switch is in the receive mode, the incomingmessage from a remote site which comprises a burst of baud sync pulsesfor a predetermined time followed by the preamble and then by themessage proper is coupled to the input of the first shift registerstage. The instant that all 49 digits of the preamble are stored in theshift register, a GO pulse will be generated or not generated, dependingon the number of errors received in the preamble. Switch 88 is apreamble stop switch and is used when the transmit-receive switch is inthe receive position.

I claim: i

1. A system for testing communications conditions between two stationscomprising:

(a) a source of clock pulses;

(b) .a preamble counter including a series of p-liops with each Hip-flophaving a pair of complementary outputs, the preamble counter beingpulsed by the source of clock pulses;

(c) means for starting the preamble counter;

(d) a diode ,matrix system having a plurality of outputs and a pluralityof inputs, one each of the inputs connected to each of the plurality ofoutputs of the preamble counter for selecting a predetermined se quenceof binary output values;

(e) an OR gate circuit fed by the plurality of outputs of the diodematrix system;

(f) a shift register having multiple outputs and fed by the OR gatecircuit;

(g) means for pulsing the shift register;

(h) means for evaluating the outputs of the shift register;

(i) and means for producing a GO signal fed by the evaluating means.

2. A system for synchronizing and evaluating communications conditionsbetween two stations comprising:

(a) a source of clock pulses;

(b) synchronizing means for generating synchronizing pulses at onestation for transmission to the other station for a predetermined time,the synchronizing means being pulsed by the source of clock pulses;

(c) means for starting the synchronizing means;

(d) a preamble counter including a series of ip-ops with each ip-ophaving a pair of complementary outputs, the preamble counter beingpulsed by the source of clock pulses;

(e) means for starting the preamble counter;

(f) a diode matrix network having a plurality of outputs and a pluralityof inputs, one each of the inputs connected to each of the plurality ofoutputs of the preamble counter for selecting a predetermined sequenceof binary output values;

(g) an OR gate circuit fed by the plurality of outputs of the diodematrix network;

(h) a shift register having multiple outputs fed by the OR gate circuitand activated by the source of clock pulses;

(i) means for pulsing the shift register;

(j) means for evaluating the outputs of the shift register;

(k) and means for producing a GO signal fed by the evaluating means.

3. A synchronizing and evaluating system according to claim 2 whereinthe synchronizing means comprise:

(a) a starting signal source;

(b) a control flip-flop having set and reset triggered by the startingsignal source;

(c) a synchronizing gated amplier fed by the source of clock pulses andthe set output of the control flip-flop, the gated amplifier having apulsed output;

(d) a second ip-flop complementarily triggered by the gated amplifier,the output of the second flip-flop being a synchronizing signal;

(e) and a series of delay flip-flops connected to the output of thesecond flip-flop, the output of the last of the plurality of delayilip-flops being fed to the control flip-flop for triggering to thereset state thereof and inhibiting the first gated amplifier.

4. A synchronizing and evaluating system according to claim wherein themeans for pulsing the shift register comprise:

(a) a first shift gated amplifier fed by the source of clock pulses andone output of the matrix network;

(b) a shift flip-flop triggered by the first shift gated amplier;

(c) a second shift gated amplifier fed by the source of clock pulses andthe output of the shift ipfflop; (d) a monostable multivibratortriggered by the second shift gated amplifier;

(e) and an edge sensitive pulse amplifier fed by the monostablemultivibrator, the output of the edge sensitive pulse amplifier beingfed to the shift register.

outputs References Cited UNITED STATES PATENTS 3,069,498 12/1962 Frank178-69 3,252,139 5/1966 Moore 340-146.1

MALCOLM A. MORRISON, Primary Examiner R. S. DILDINE, JR., AssistantExaminer U.S. Cl. X.R.

